1. Field of the Invention
The present invention relates to arithmetic and logic circuits in general and to a multiple cell CMOS arithmetic logic unit comprising carry-bypass and active restore circuitry for providing outputs corresponding to selected arithmetic and logic operations in particular.
2. Description of Prior Art
Logic circuits comprise arrays of transistors which are responsive to combinations of data bits for providing one or more outputs corresponding to predetermined logical operations performed on the data bits. In a multiple logic operation circuit of the type to which the present invention relates, the selection of the logical operation to be performed on the data bits is typically controlled by a plurality of control or code bits.
An arithmetic unit comprises an array of transistors which is responsive to the bits of a first and a second operand for providing one or more outputs corresponding to selected arithmetic operations such as addition and subtraction.
Typically, a subtraction operation is performed by adding the two's complement of one of the operands, i.e. the subtrahend, to the positive value of the other operand, i.e. the minuend.
In general, an addition operation involves a circuit for providing a carry bit. Since, as described above, a subtraction operation is actually an addition operation as far as the arithmetic unit is concerned, it is apparent that both the addition and the subtraction operations involve the use of a carry bit circuit.
Heretofore, circuits for providing carry bits in an addition operation typically comprise either the well known Manchester-type carry chain circuit or a circuit which comprises a carry-look-ahead technique. However, both of these types of circuits have certain well known disadvantages.
In a multiple cell arithmetic unit comprising a Manchester-type carry chain circuit, the propagation of the carry bit from the least significant bit cell to the most significant bit cell requires the carry bit to be propagated from one cell to another through one or more transistors in each cell. Since each transistor through which the carry bit is propagated delays the propagation of the carry bit, the number of cells in the chain determines the maximum propagation delay of the carry bit in the circuit. For example, in a 32 cell arithmetic unit for operating on 32 bit operands comprising 32 pass gates for propagating a carry bit from the least significant bit cell to the most significant bit cell, the propagation delay in the carry chain corresponds to 32 gate delays. Such delays result in an undesirably long time to perform an addition operation.
The principal disadvantage of arithmetic units which comprise the carry-look-ahead technique is that a typical implementation of the technique requires an undesirably large number of transistors and a correspondingly large loading in the driver stages.
In many transistor circuits, particularly those comprising CMOS transistors, the turn-on time of the transistor is typically significantly longer than the turn-off time. Consequently, multiple cell arithmetic units comprising circuits which rely on turning on a transistor for propagating a carry bit from a least significant bit cell to a most significant bit cell result in undesirably long carry bit propagation delays.